1. Field of the Invention.
The present invention relates to a semiconductor memory device and manufacturing method thereof, and more particularly to a semiconductor memory device and manufacturing method thereof, having improved cell stability, low power dissipation and increased cell immunity to soft errors.
2. Description of the Related Art.
Research in the field of static random access memory (SRAMs) devices is now being conducted to take advantage of the latest advances in semiconductor technology. SRAM memory cells are presently manufactured consisting essentially of two transfer transistors, two driving transistors and two load elements.
Although SRAM memory capacity is smaller than that of dynamic random access memories (DRAMs), SRAMs are employed in various applications requiring memory including small and medium scale systems, such as microcomputer systems or terminals. SRAMs are easy to handle and operate quite efficiently even for high speed operations. SRAMs are generally classified into one of three types relating to the type of load element selected. A depletion load-type memory cell uses a depletion-mode NMOS transistor which serves as the load. A polysilicon-type load memory cell employs high-resistant polysilicon instead. A CMOS-type load memory cell uses a PMOS transistor.
The depletion load-type memory cell, however, is rarely employed in memory devices having greater than 16 Kbit capacity given its characteristic high power consumption.
While the CMOS-type memory cell can markedly decrease power dissipation, its cell area is larger than the other two types and in normal operation it is susceptible to a latch-up phenomenon which restricts its utilization. Until recently, the trend was towards use of high-resistant polysilicon load-type memory cell SRAMs in a wide number of applications. High-resistant polysilicon load-type memory cells, such as shown in FIG. 1, have a relatively simple manufacturing process and exhibit low power dissipation when the resistance of the polysilicon is increased.
In addition, when three dimensionally arranging each high-resistant polysilicon load with respect to its corresponding driving transistor, memory cell area is substantially decreased.
For these reasons, the high-resistant polysilicon load-type memory cell is most suitable for large-scale integrated SRAMs.
Recent developments in the CMOS technique, however, have led designers to reevaluate the usefulness of the CMOS-type memory cell SRAM. The prospect of such devices consists of having a non-volatile CMOS-type memory cell SRAM provided with a battery back-up system. Such a device would be capable of retaining previously stored information despite possible power supply interruptions, given its remarkably low power dissipation in a standby mode of operation.
By further introducing silicon-on-insulator (SOI) techniques into the design of CMOS-type memory cell SRAMs, cell area can be further reduced by taking advantage of developments in three-dimensional CMOS manufacturing techniques.
In addition, because numerous problems were encountered during manufacture of high-packing density high-resistant polysilicon load-type memory cell SRAMs, the CMOS-type load memory cell SRAM architecture is beginning to gain great appeal among SRAM designers.
In order to manufacture a low power dissipation SRAM of high-resistant polysilicon load-type memory cells of 4M bit or greater packing density, the effective resistance of the polysilicon material employed as the load element must be increased.
However, a resistance of more than approximately 10 T.OMEGA. is required to maintain a standby current of approximately 1 .mu.A in a 4 Mb SRAM type cell, at which point charging current supplied to the cell decreases abruptly, thereby impeding cell stability.
In addition, the resistance of the polysilicon material must be approximately 100 T.OMEGA. at room ambient temperatures in order to maintain a resistance of above 10 T.OMEGA. in standby mode. Such tolerances present difficulties in the manufacturing process, particularly if a supply voltage is decreased to prevent degradation due to hot carriers.
Similarly, the supply current and junction leakage current may approach equivalency which results in an increase in soft-error rate.